Communication system for the handicapped

ABSTRACT

A seven-key hard wire controller with a dual-sequence operation is used to provide an output signal for producing a typed symbol or the like. When used in a matrix arrangement, the first actuation of one of the switches will provide an X-coordinate, and the second actuation of one of the switches will provide the Y-coordinate. Circuitry is provided to store the X-coordinate signal until the second switch actuation occurs. Upon release of the second switch of the actuated pair, the symbol is typed or the desired function is activated, and the system is reset to accept another pair of inputs. The system is compatible with most types of electric typewriters, adding machines and punched and magnetic tape devices, as well as almost any machine where data or information is to be stored, printed, displayed or otherwise used.

United States Patent 1191 Kafafian [451 Aug. 20, 1974 COMMUNICATIONSYSTEM FOR THE HANDICAPPED [21] App]. No.: 220,995

Primary ExaminerHar0ld I. Pitts Attorney, Agent, or Firm-Bacon & Thomas[5 7] ABSTRACT A seven-key hard wire controller with a dual-sequenceoperation is used to provide an output signal for producing a typedsymbol or the like. When used in a ma- 52 US. Cl. 340/166 R arrangementthe first actuation of one of 51 Int. Cl. H04q 3/00 Switches WillProvide x-cofrdinate, and the Second [58] Field Of Search 340/166 Ractuation of one of the switches Will Provide the coordinate. Circuitryis provided to store the X- [56] References Cited coordinate signaluntil the second switch actuation oc- UNITED STATES PATENTS curs. Uponrelease of the second switch of the actuated pair, the symbol is typedor the desired function g is activated, and the system is reset toaccept another 3' 11 69 g zs 3405166 UX pair of inputs. The system iscompatible with most 41 H970 'x 340/166 UX types of electrictypewriters, adding machines and 3:55 1:888 12/1970 Balugani 340/166 RPunched and magnetic tape devices as as almost 3,573,388 4/1971 pagna340/166 R any machine where data or information is to be 3,582,8926/1971 Juliusburger 340 1 R stored, printed, displayed or otherwiseused. 3,593,289 7/1971 Lerch 340/166 X 7 Cl 3 D F. 3,597,737 8/1971Wallace 340/166 R 1756/ H /NP//T fil/FFEI? U/ C/ACU/T j X%0H7IZIQI//N7@TE 2 I562 E +V liv 1 1.. T Ll/Vk A x-coammqrs D2 5205/751057- 4+ 5W3 722 156,3 6 Z34 0520/7 5 3 F l 03 Q I 6W4 r5614 5 Z44l0 4? 4 4 K F LAMP Z/ZH Y-CO0FDIM4 TE 04 e) OUTPUT I I565 E A ycameg/Nxir5 L/NE 5W5 -2- 04 E FJJL 12 5 i" 5 C/ACU/T z;

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comma/v /NPl/T :D 6/56 i BUFFEP C/ALl/ll' (T swa Cl 1 t? r5v- Z/ZG ICOMMUNICATION SYSTEM FOR THE I-IANDICAPPED BACKGROUND OF THE INVENTIONThe present invention relates to an improvement in systems for operatingtypewriters and other programcontrolled machines which are particularlyadapted for use by the blind, amputees, and those afflicted withdebilitating diseases such as multiple sclerosis and cerebral palsy.Reference is made here to the extensive introductory portion in myprevious US. Pat. No. 3,507,376 which will provide additional backgroundinformation upon which that invention, as well as the instant invention,is based.

The operation of the system set out in my previous patent required agreater amount of manual dexterity than is often possessed by somehandicapped persons. Also, due to certain disabilities in some persons,a system is needed having easier methods of actuation. At the same timeit is desirable that the operator be required to exert as much movementas he is capable of, where required for therapeutic purposes.

In addition to my earlier patent, several others are worthy of note.Tevis, US. Pat. No. 2,031,017, illustrates a device having a number ofinput keys equivalent to the number of digits on a persons hand used toprovide the X- and Y-coordinate inputs to actuate a plurality ofsolenoids representative of the keys on a typewriter, but theirnature'limits its utility.

Another communication device is illustrated in Seibel et al., U.S. Pat.No. 3,022,878, which discloses a machine control system designedespecially for aerospace applications wherein the operator is equippedwith a three-position transducer for each finger and is required toperform small movements of hisfingers in order to actuate the controlsof the machine.

The high degree of manual dexterity in the abovementioned systems andthe high costs of manufacturing and of maintenance are the principalshortcoming thereof. The same is true of much of the other prior art,

such as US. Pat. Nos. 2,532,228; 2,573,370; 2,613,797; 2,924,321;3,166,856; 3,239,664 and 3,241,115.

SUMMARY OF THE INVENTION The present system is of the hard wire type,and a seven-key controller or logic box contains the electroniccircuitry required to convert a seven-key dualsequential input to a 7 X7 dual-concurrent output or other known input/output devices for theultimate control of a typewriter, other business machines, or the like,or other programmable machines. The sequential momentary actuation ofany two of the seven interface key-operated coding switches, which caninclude a repeat actuation of the very same switch, will produce anoutput from the controller.

A signal resulting from the actuation of the first interface switch ofthe sequentially operated pair is stored or time delayed, and is theX-coordinate of a 7 X 7 matrix. When the second switch is actuated, a Y-coordinate signal of the 7 X 7 matrix and the X- coordinate retrievedfrom storage are provided as outputs from the seven-key logic box. Uponrelease of the second switch of the actuated pair the logic circuitry isreset, the memory is cleared, andthe logic box is ready to acceptanother sequentially paired input. The circuitry in the matrix cancontrol a typewriter, or the X, Y-coordinates can be fed into aconverter which will in turn control a ball typewriter such asmanufactured by IBM under the trademark SELECTRIC," or a teleprinter orthe like, e.g., input/output typwriter, or display.

. BRIEF DESCRIPTION OF THE DRAWINGS The novel features of the inventionare set forth in the appended claims. The invention itself, both as toits construction and manner of operation, together with additionalobjects and advantages thereof, will be understood from the followingdescription of the preferred embodiments when read in conjunction withthe accompanying drawing wherein:

FIG. 1 is a schematic diagram of a seven-key controller;

FIG. 2 is a block schematic showing the output from FIG. 2 feeding intoa matrix arrangement which in turn controls a typewriter; and

FIG. 3 is a block schematic showing the outputs from FIG. 1 feeding intoan ASCII code converter and solenoid driver, which in turn controls atypewriter.

DETAILED DESCRIPTION OF THE INVENTION Reference is now made to FIG. 1wherein there are illustrated seven interface coding switching means ortransducers S Wl-SW7. Energization of each switch feeds a signal overlines 1-1 to 1-7 into respective input buffer circuits lCBl-ICB7.Likewise, the energization of any of the switches SW1-SW7 also connectsthe potential to a common input buffer CIBC through a plurality of lines2-1 to 2-7 and diodes Dl-D7. As will be seen below, CIBC changes stateprior to [CB 1-ICB7 on actuation of the switch and reverts to the staticstate after ICBl-ICB7 on switch release. The outputs from the inputbuffer circuits ICBl-ICB7 are fed over lines 3-1 to 3-7 to respectiveX-coordinate input drive gates ZlA through Z7A. It will be noted thatlines 3-1 through 3-7 are connected to one of the terminals of theinputAND gates ZlA-Z7A. The other terminal of input AND gate is connected bya common line 4 as will be discussed below. The output of each inputgate ZlA through Z7A is connected to one of the inputs of a respectivenumber of first switch memory binaries ZlB through Z7B. One output, 5-1through 5-7, from each of the first switch memory binaries ZlB thorugh27B is connected to a logic element Z8. The logic element Z8 changesstate the instant a first bit representing a first switch actuation isloaded in one of the memoriesZlB-Z7B. Each of the memories Z1B-Z7B havea second output 6-1 through 6-7 (also labeled A-G') connected to arespective X-coordinate output drive circuit 7 (only one of which isseen). The drive .circuits are in turn directlyconnected to X-coordinateoutput lines, one of which is seen at 8.

One output from logic element Z8 is connected to a lamp driver circuit10 which will illuminate a first bit indicator 12 which may be placedadjacent the interface panel to provide the operator with feedback tothe effect that the first bit has been accepted and is stored in thememory. The output of element Z8 is also connected via a line 26 to line4 through an inverter 29D which in turn is connected to the second ofthe input terminals of drive gates Z1A-Z7A, closing them. Line 26 isalso connected to control binary Z9B.

When any one of the switches SW1-SW7 is released, an output from thecommon input buffer circuit CIBC places a signal on line 14 through aninverter Z12A to a logic AND gate element Z9A. There will also be anoutput from logic element Z8 over line 16 into AND gate Z9A. When theswitch is released, therefor, there will'be outputs over lines 14 and16, thus gating logic element Z9A on, which in turn will gate on acontrol binary labeled Z9B. The output of the control binary Z9B will befed over a line 18 to one terminal of a plurality of Y-coordinate drivergates Z12A-Z12G. The other input terminal of each of the logic elementsZ12A-Z12G will be connected to respective output lines A-G of the inputbuffer circuit, one of which is seen as line 20. Each of theY-coordinate drive gates when gated on will transmit a signal to theappropriate Y-coordinate driver circuit, one of which is seen as 22. Theoutput of the Y-coordinate driver circuit is connected directly to aY-coordinate output line 23.

As will be discussed more fully below in the OPER- ATION section, itwill be seen that actuation of the second switch of the sequential pairproduces an output from its associated input buffer circuit IBC1-IBC7which is transmitted to the appropriate Y-coordinate output drivercircuit (for example 22) through the enabled drive Y-coordinate drivergate Zl2A-Zl2G.

The X and Y coordinate output lines may be connected to matrix 30 suchas that shown in my previous US Pat No. 3,507,376. This is schematicallyshown in FIG. 2. Thus, a dual-sequential input is converted to adual-concurrent output. Alternatively, as seen in FIG. 3, outputs 8 and23' may be connected to a code converter, such as an ASCII codeconverter, and a solenoid driver-or some other logic conversionsystem--to operate a typewriter, such as the IBM SELECTRIC brandtypewriter.

Upon release of the second switch of the sequentially operated pair, thetransition of the output from CIBC to its static state is differentiatedby the network 21 at the input of logic element Z10C. The other terminalof 210C is connected to the output of control binary 298 via line 34through an inverter 213A. The pulse output from 210C is connected to oneof the terminals of logic OR element 211C. The output from 211C resetsthe first switch memory binaries ZlB-Z7B. With the first binaries reset,Z8 reverts to its initial static state, and the first-bit light 12 isextinguished. Also, the static state of 28 through line 26 is used toreset the control binary 298. Thus, the controller is ready to acceptanother dual sequential input.

Also, the binaries Z1B-Z7B, and thus the control binary Z9B, areintially reset when the device is turned on through element Zl1C vialine 28. This is accomplished from the volt potential which is delayedthrough the charging action of C 1.

Also, the firstswitch memory binaries can be reset through Z11C uponactuation of SW8 in the event the operator recognizes that his firstinput switch selection was an error.

OPERATION OF THE INVENTION For ease in explanation it is assumed thatthe operator pressesswitch SW1 for his first sequential pairenergization, which will provide the X-coordinate, and then also pressesSW1 to provide the Y-coordinate. The present system operates inreal-time, and features direct memory access.

When the device is turned on the binaries Z1B-Z7B are initially resetthrough element Z1 1C. The closing of switch SW1 will feed the signalinto input buffer circuit lBCl over line l-l. The output from inputbuffer circuit IBCl will go over the line 3-1 into the X-coordinatedrive input gate ZlA at its first terminal. The signal will also appearon the common input buffer circuit CIBC over line 2-1 through D1.

Now assuming that the drive gate 21A is enabled by the signal comingover line 4, the signal from SW1 will be impressed upon the first switchmemory binary ZlB. The signal will be generated over line 5-1 to logicelement Z8 which will change its state the instant the bit ofinformation is loaded into memory binary 213.

The output from Z8 over line 26 through element Z9D will then gate ofthe various elements ZlA-Z7A. The Z8 output, which, is also connected tothe lamp driver 10, will illuminate the first bit indicator 12 to advisethe operator that the X-coordinate has been established.

The establishment of the X-coordinate is accomplished by thetransmission of a signal over line 6-1 (also labeled A) to theX-coordinate output drive circuit 7 and then on to the X-coordinateoutput line 8.

Upon release of the switch SW1 an output signal from the common inputbuffer circuit CIBC places an input signal over line 14 to one terminalof the logic element 29A. The other terminal of element 29A is energizedvia line 16 from logic element Z8. Therefore, when the switch isreleased there will be outputs over lines 14 and 16, thus gating logicelement Z9A on. Because of the timing relationship between the output oflCBl and CIBC, the switching on of 29A is assured of occuring afterICBl. This in turn will latch the control binary Z9B. Since the outputof control binary 29B is connected to one of the terminals of logicelements Z12A-Z12G, one terminal will be gated on for each of theelements which are the Y-coordinate drive gates. When the switch isdepressed for the second time (again assuming it is the switch SW1), thesignal will follow over lines 1-1 to the input buffer circuit lBCl andline 3-1 to line 20 (also labeled A). Since the Y-coordinate drive gateshave been enabled via line 18, the output from line 20 will thus gate onthe logic element Z12A. This in turn will energize the Y-coordinatedriver circuit 22 and provide an output on the Y- coordinate output line23.

Now upon release of the second switch the reversion to the initialstatic state of the output over line 14 from the common input buffercircuit CIBC will be differentiated by element 21 and energize logicgate 210C, which has been enabled by the control binary 29B. This signalis utilized to clear the memory binaries Z1B Z7B through logic elementZ1 1C, which will output a reset signal to the memory binaries over line28.

With the first switch binaries reset, Z8 reverts to its initial staticstate, and the first bit light 12 is extinguished. Also, the staticstate of Z8 through line Z6 is used to reset the control binary Z9B.

Reset switch SW8 can also be used in conjunction with logic element Z11C to reset the first switch memory binaries ZlB-Z7B when an error ismade in actuation of the first switch.

The output from X- and Y-coordinate lines 8 and 23 are connected tomatrix 30 or code converter 32 for for example.

The hard wire control system of invention is thus seen to utilize directaccess to the memory, and to operate in real-time'lt is to be understoodthat the number of input switches can be varied in the system, accordingto a formula whereby the number of resultant signals is equal to S",wherein S is the number of input switches and n is the number ofsuccessive sequential actuations.

While a specific form of the invention has been described herein, it isto be understood that the same is merely illustrative of the principlesinvolved and that other forms may be resorted to within the scope of theappended claims.

I claim:

1. In a hard wire direct access control operating in real time:

a. a single set of at least two input switching means;

b. logic means for providing single X and Y outputs registeringsuccessive, sequential actuations of said single set of switching means,said logic means including means for first storing a signal commensuratewith a first actuation, and means for generating a Y output signalcommensurate with a second actuation together with an X output signalcommensurate with the first stored signal only after initiating thesecond actuation; and

c. utilization means connected to said outputs for providing a singleresultant indication representative of the combination of the successiveactuations of said switching means in real time.

2. In a control as defined in claim 1, wherein said utilization means isa typewriter.

3. In a control as defined by claim 1, wherein the number of resultantindications is equal to S wherein S is the number of input switchingmeans and n is the number of successive sequential actuations.

4 in a control as defined in claim 3, including means for resetting saidlogic means prior to the nth switch actuation whereby no outputwilloccur until said switching means receives it switch actuations.

5. In a control as defined in claim 1, in means for indicating theoccurrence of a first switch actuation.

6. In a control as defined in claim 1 including:

a. an input buffer circuit connected to each of said switching means;

b. an X-coordinate input drive gate connected to each of said inputbuffer circuits;

c. a first switch memory connected to each of said X- coordinate inputgates;

d. an X-coordinate output drive circuit connected to each of said firstswitch memory;

e. a utilization circuit having X and Y inputs thereto;

f. an X-coordinate output line for each of said X- coordinate outputdrive circuits connected to an X input of said utilization circuit;

g. a Y-coordinate input drive gate also connected to each of said inputbuffer circuits;

h. a Y-coordinate output drive circuit connected to each of saidY-coordinate input drive gates;

i. a Y-coordinate output line for each of said Y- coordinate outputdrive circuits connected to a Y input of said utilization circuit;

j. means for enabling said X-coordinate drive gate for passingtherethrough a first switch actuation signal, and means for disablingsaid X-coordinate drive gate after said first switch actuation is storedin said first switch memory; and

k. means for disabling said Y-coordinate drive gate during said firstswitch actuation and means for enabling said Y-coordinate drive gateafter said first switch actuation.

7. In a control as defined in claim 1, wherein there are seven inputswitching means.

1. In a hard wire direct access control operating in real time: a. asingle set of at least two input switching means; b. logic means forproviding single X and Y outputs registering successive, sequentialactuations of said single set of switching means, said logic meansincluding means for first storing a signal commensurate with a firstactuation, and means for generating a Y output signal commensurate witha second actuation together with an X output signal commensurate withthe first stored signal only after initiating the second actuation; andc. utilization means connected to said outputs for providing a singleresultant indication representative of the combination of the successiveactuations of said switching means in real time.
 2. In a control asdefined in claim 1, wherein said utilization means is a typewriter. 3.In a control as defined by claim 1, wherein the number of resultantindications is equal to Sn, wherein S is the number of input switchingmeans and n is the number of successive sequential actuations. 4 In acontrol as defined in claim 3, including means for resetting said logicmeans prior to the nth switch actuation whereby no output will occuruntil said switching means receives n switch actuations.
 5. In a controlas defined in claim 1, in means for indicating the occurrence of a firstswitch actuation.
 6. In a control as defined in claim 1 including: a. aninput buffer circuit connected to each of said switching means; b. anX-coordinate input drive gate connected to each of said input buffercircuits; c. a first switch memory connected to each of saidX-coordinate input gates; d. an X-coordinate output drive circuitconnected to each of said first switch memory; e. a utilization circuithaving X and Y inputs thereto; f. an X-coordinate output line for eachof said X-coordinate output drive circuits connected to an X input ofsaid utilization circuit; g. a Y-coordinate input drive gate alsoconnected to each of said input buffer circuits; h. a Y-coordinateoutput drive circuit connected to each of said Y-coordinate input drivegates; i. a Y-coordinate output line for each of said Y-coordinateoutput drive circuits connected to a Y input of said utilizationcircuit; j. means for enabling said X-coordinate drive gate for passingtherethrough a first switch actuation signal, and means for disablingsaid X-coordinate drive gate after said first switch actuation is storedin said first switch memory; and k. means for disabling saidY-coordinate drive gate during said first switch actuation and means forenabling said Y-coordinate drive gate after said first switch actuation.7. In a control as defined in claim 1, wherein there are seven inputswitching means.